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ds087 (v1.2) june 7, 2002 www.xilinx.com 1 advance product specification 1-800-255-7778 ? 2002 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. summary ? system level, high capacity, pre-configured solution for virtex? series fpgas, virtex-ii series platform fpgas, and spartan? fpgas industry standard flash memory die combined with xilinx controller technology in a single package effortless density migration: - xccacem16-bg388i (16 megabit (mb)) - XCCACEM32-BG388I (32 mb) - xccacem64-bg388i (64 mb) all densities are available in the 388-pin ball grid array package vcc i/o: 1.8v, 2.5v, and 3.3v configuration rates up to 152 mb per second (mb/s) flexible configuration solution: - selectmap (control up to four fpgas) - slave-serial - concurrent slave-serial (up to eight separate chains) patented compression technology (up to 2x compression) jtag interface allows: - access to the standard flash memory - boundary scan testing native interface to the standard flash memory is provided for: - external parallel programming - processor access to unused flash memory locations supports up to eight separate design sets (selectable by mode pins or via jtag), enabling systems to reconfigure fpgas for different functions compatible with ieee standard 1532 user-friendly software to format and program the bitstreams into the standard flash via the patented flash programming engine internet reconfigurable logic (irl) upgradeable system description the system ace multi-package module (mpm) solution addresses the need for a space-efficient, pre-engineered, high-density configuration solution in multiple fpga sys- tems. the system ace technology is a ground-breaking in-system programmable configuration solution that pro- vides substantial savings in development effort and cost per bit over traditional prom and embedded solutions for high capacity fpga systems. as shown in figure 1 , the system ace mpm solution is a multi-package module that includes the system ace mpm controller, a configuration prom, and an amd flash memory. the system ace mpm has four major interfaces. (see figure 2 .) the boundary scan jtag interface is provided for boundary scan test and boundary-scan-based flash mem- ory programming. the system control interface provides an input for the system clock, design set selection pins, system configuration control signals, and system configuration sta- tus signals. the native flash memory interface provides direct read and write access to the flash memory unit. the target fpga interface provides the signals to configure target fpgas via the slave-serial, concurrent slave-serial, or selectmap configuration modes. separate power pins provide voltage compatibility control for the target fpga configuration interface and for the sys- tem control/status interface. see figure 3 for a complete view of the components and schematic of the signals in the system ace mpm. 0 system ace? mpm solution ds087 (v1.2) june 7, 2002 00 advance product specification r
system ace ? mpm solution 2 www.xilinx.com ds087 (v1.2) june 7, 2002 1-800-255-7778 advance product specification r figure 1: system ace mpm assembly 16/32/64 mbit amd flash memory package: 48 pin tsop dimensions: 20 x 12 x 1.2 mm prom xc18v01 package: vq44 dimensions: 12 x 12 x 1.2 mm virtex xcv50e configuration controller package: cs144 dimensions: 12 x 12 x 1.2 mm metal lid mpm bga module system ace mpm bg388 complete assembly dimensions: 35 x 35 x 2.7 mm ds087_01_081501 figure 2: system ace mpm interfaces system ace mpm prom slave-serial or selectmap amd flash memory boundary scan interface system control interface native flash memory xcv50e configuration controller target fpga interface ds087_02_091001
system ace ? mpm solution ds087 (v1.2) june 7, 2002 www.xilinx.com 3 advance product specification 1-800-255-7778 r figure 3: system ace mpm schematic amd flash v io /byte * 2 acc * 4 reset a0-a21 * 1 dq0-dq15 oe ce we acc/wp * 5 ry/by * 3 tdi tck tms tdo reset * 6 flash_io_level* 2 acc * 4 a0-a21 * 1 dq0-dq15 oe ce we wp * 5 ry/by * 3 fcm_enable flash_vcco cfg_vcco ctrl_vcco xcv50e tdi cclk din init done program sysreset sysclk bitstrsel[0-2] status[0-3] cfg_mode[0-2] cfg_clk cfg_busy cfg_init cfg_done cfg_prog cfg_write cfg_cs[0-3] cfg_data[0-7] tck tms tdo reset a0-a21 * 1 dq0-dq15 oe ce we wp * 5 ry/by * 3 fcm_enable vcco 2,3,4,5 vcco 6,7 vcco 0,1 4.7k *1 a21 for xccacem64 only; a20 for xccacem32 and xccacem64 only. *2 v io for xccacem64; byte for xccacem16 and xccace32. *3 xccacem16 and xccacem32 only. *4 xccacem64 only. *5 wp on xccacem64; acc/wp on xccacem32. do not apply v to acc/wp. *6 do not apply v id to reset. xc18v01 tck tms tdo clk d0 oe/reset ce cf tdi 300 4.7k 3.3v 3.3v gnd system ace mpm devrdy fcmreset sysreset sysclk bitstrsel[0-2] status[0-3] cfg_mode[0-2] cfg_clk cfg_busy cfg_init cfg_done cfg_prog cfg_write cfg_cs[0-3] cfg_data[0-7] ds087_03_091701 hh
system ace ? mpm solution 4 www.xilinx.com ds087 (v1.2) june 7, 2002 1-800-255-7778 advance product specification r pin descriptions this section provides native flash interface, boundary scan, and target fpga configuration pinout information. native flash interface pins all of the native flash memory pins are routed to pins on the system ace mpm ball-grid-array. thus, the flash memory is available to the system for direct read and write access with a few restrictions. see note 1 and table 1 for descrip- tions of the restrictions. notes: 1. all of the native flash memory interface pins are connected to the system ace mpm controller (except where explicitly noted in the pin description). the fcm_enable pin must be held low to externally access the flash memory without contention with the system ace mpm controller. boundary scan pins the system ace mpm controller (virtex-e xcv50e) and the system ace mpm controller prom (xc18v01) are both ieee standard 1149.1 compatible devices. the sys- tem ace mpm connects these devices into an internal scan chain comprised of the xc18v01 device followed by the xcv50e device. the internal scan chain is accessible through the boundary scan test access port (tap) on the bg388 package. see ta bl e 2 . table 1: native flash memory interface pins pin name pin type description a0-a21 i/o flash memory address bus. a21 exists on the xccacem64 only. a20 exists on the xccacem32 and xccacem64 only. dq0-dq15 i/o flash memory data bus. dq15 becomes the a-1 pin in the xccacem16 and xccacem32 when the byte mode is active. reset i/o flash memory hardware reset. when asserted, all flash operations are immediately terminated and flash is reset to read mode. when reset and ce are held high, the flash memory is put into standby mode. do not apply v id to the reset pin. the reset is connected to the system ace mpm controller that has a maximum tolerance of 3.6 v. ce i/o flash memory chip enable. when reset and ce are held high, the flash memory is put into standby mode. oe i/o flash memory output enable. we i/o flash memory write enable. ry/by output flash memory ready/busy signal. open-drain output. when low, the rd/by signal indicates that the flash is actively erasing, programming, or resetting. xccacem16 and xccacem32 only. wp i/o flash memory hardware write protect. acc input flash memory accelerated mode pin. do not apply v hh to the xccacem32 wp/acc pin. the xccacem32 wp/acc pin is connected to the system ace mpm controller that has a maximum tolerance of 3.6 v. the xccacem64 acc pin is independent of the rest of the system ace mpm and may be used to put the flash memory into accelerated program operation. flash_io_level input flash memory v io pin on the xccacem64 only. this pin must be connected to 3.3v for compatibility with the system ace mpm controller. byte input flash memory byte-wide data bus mode. xccacem16 and xccacem32 only. this pin must be connected to 3.3v for compatibility with the system ace mpm controller and thus only the 16-bit, word mode is available for accessing the flash memory in the system.
system ace ? mpm solution ds087 (v1.2) june 7, 2002 www.xilinx.com 5 advance product specification 1-800-255-7778 r target fpga configuration pins ta ble 3 provides target fpga configuration pins. table 2: ieee 1149.1 boundary scan pins pin name pin type description tck input ieee 1149.1 test clock pin. the system ace mpm tck pin is connected to the xcv50e and xc18v01 tck pins. by default, the xcv50e has an internal pull-up resistor on its tck pin. tms input ieee 1149.1 test mode select pin. the system ace mpm tms pin is connected to the xcv50e and xc18v01 tms pins which have internal pull-up resistors. tdi input ieee 1149.1 test data input pin. the system ace mpm tdi is connected to the xc18v01 tdi pin which has an internal pull-up resistor. tdo output ieee 1149.1 test data output pin. the system ace mpm tdo pin is connected to the xcv50e tdo pin which by default has an internal pull-up resistor. table 3: target fpga configuration pins pin name pin type description cfg_data[0] output for slave-serial configuration mode, cfg_data[0] is the serial data signal for serial-slave chain 0 and is connected to din of the first fpga in the slave-serial chain 0. for slave-selectmap configuration mode, cfg_data[0] is the data bit 0 on the selectmap bus and is connected to d0 on all target fpgas. cfg_data[1] output for slave-serial configuration mode, cfg_data[1] is the serial data signal for serial-slave chain 1 and is connected to din of the first fpga in the slave-serial chain 1. for slave-selectmap configuration mode, cfg_data[1] is the data bit 1 on the selectmap bus and is connected to d1 on all target fpgas. cfg_data[2] output for slave-serial configuration mode, cfg_data[2] is the serial data signal for serial-slave chain 2 and is connected to din of the first fpga in the slave-serial chain 2. for slave-selectmap configuration mode, cfg_data[2] is the data bit 2 on the selectmap bus and is connected to d2 on all target fpgas. cfg_data[3] output for slave-serial configuration mode, cfg_data[3] is the serial data signal for serial-slave chain 3 and is connected to din of the first fpga in the slave-serial chain 3. for slave-selectmap configuration mode, cfg_data[3] is the data bit 3 on the selectmap bus and is connected to d3 on all target fpgas. cfg_data[4] output for slave-serial configuration mode, cfg_data[4] is the serial data signal for serial-slave chain 4 and is connected to din of the first fpga in the slave-serial chain 4. for slave-selectmap configuration mode, cfg_data[4] is the data bit 4 on the selectmap bus and is connected to d4 on all target fpgas. cfg_data[5] output for slave-serial configuration mode, cfg_data[5] is the serial data signal for serial-slave chain 5 and is connected to din of the first fpga in the slave-serial chain 5. for slave-selectmap configuration mode, cfg_data[5] is the data bit 5 on the selectmap bus and is connected to d5 on all target fpgas.
system ace ? mpm solution 6 www.xilinx.com ds087 (v1.2) june 7, 2002 1-800-255-7778 advance product specification r pin name pin type description cfg_data[6] output for slave-serial configuration mode, cfg_data[6] is the serial data signal for serial-slave chain 6 and is connected to din of the first fpga in the slave-serial chain 6. for slave-selectmap configuration mode, cfg_data[6] is the data bit 6 on the selectmap bus and is connected to d6 on all target fpgas. cfg_data[7] output for slave-serial configuration mode, cfg_data[7] is the serial data signal for serial-slave chain 7 and is connected to din of the first fpga in the slave-serial chain 7. for slave-selectmap configuration mode, cfg_data[7] is the data bit 7 on the selectmap bus and is connected to d7 on all target fpgas. cfg_mode[0] output the cfg_mode pins set the configuration mode on the target fpgas. connect cfg_mode[0] to the m0 pin on all target fpgas. cfg_mode[1] output the cfg_mode pins set the configuration mode on the target fpgas. connect cfg_mode[1] to the m1 pin on all target fpgas. cfg_mode[2] output the cfg_mode pins set the configuration mode on the target fpgas. connect cfg_mode[2] to the m2 pin on all target fpgas. cfg_cclk output cfg_cclk is the configuration clock source for the target fpgas. the cfg_cclk is derived from the sysclk. the cfg_cclk frequency is half the sysclk frequency. connect cfg_cclk to the cclk pin on all target fpgas. cfg_prog output cfg_prog is pulsed low at the beginning of the configuration download to reset the configuration state of the target fpgas. cfg_prog is connected to the prog_b pin on all target fpgas. cfg_init input target fpga init monitor pin. at the start of the configuration process, the system ace mpm controller waits for init to go high before initiating delivery of configuration data through the cfg_data pins. cfg_init is connected to the init pin on all target fpgas. cfg_busy input when cfg_busy is high, the cfg_data outputs are held. if the target fpga configuration mode is slave-selectmap and if the cfg_cclk is greater than 50 mhz, connect the cfg_busy pin to the busy pin on all target fpgas. otherwise, pull-down the cfg_busy pin to gnd. cfg_done input cfg_done monitors the done status on all target fpgas. connect the cfg_done to the done pin on all target fpgas. done must be pulled high with an external 330- ? pull-up resistor. the bitgen option drivedone should be left in the default ? no ? setting when generating bitstreams for xilinx fpgas. cfg_write output slave-selectmap write-enable pin. connect the cfg_write pin to the rdwr_b pin on all target fpgas. cfg_cs[0] output slave-selectmap chip-enable for target fpga 0. connect the cfg_cs[0] pin to the cs_b pin on target fpga 0. cfg_cs[1] output slave-selectmap chip-enable for target fpga 1. connect the cfg_cs[1] pin to the cs_b pin on target fpga 1. cfg_cs[2] output slave-selectmap chip-enable for target fpga 2. connect the cfg_cs[2] pin to the cs_b pin on target fpga 2. cfg_cs[3] output slave-selectmap chip-enable for target fpga 3. connect the cfg_cs[3] pin to the cs_b pin on target fpga 3. table 3: target fpga configuration pins (continued)
system ace ? mpm solution ds087 (v1.2) june 7, 2002 www.xilinx.com 7 advance product specification 1-800-255-7778 r system control and status pins table 4 provides system control and status pins. power and ground pins the system ace mpm requires at least two power sup- plies: 1.8v supplies power to the system ace mpm config- uration controller (an xcv50e) core; and 3.3v supplies power to the flash memory and configuration controller prom (an xc18v01). additional power supplies may be required for the output voltage compatibility pins: flash_vcco, cfg_vcco, and ctrl_vcco. see figure 4 and table 5 for a description of the system ace mpm power pins. table 4: system control and status pins pin name pin type description fcm_enable input system ace mpm controller enable. when this pin is held low, all of the system ace mpm controller (xcv50e) pins tied to the flash memory are 3-stated allowing external peripherals access to flash memory without contention. fcmreset input system ace mpm fpga reset pin. the fcmreset pin is connected to the xcv50e program pin. applying a low pulse to the fcmreset resets the xcv50e and forces the xcv50e to reconfigure itself from the xc18v01 prom. (the xcv50e automatically configures itself from the xc18v01 prom at power-up.) devrdy output system ace mpm fpga done pin. the devrdy pin is connected to the xcv50e done pin. when devrdy is high, the xcv50e is configured and ready for operation. sysclk input sysclk is the system clock input for the system ace mpm control logic. sysreset input hold sysreset high for at least 10 sysclk cycles to reset the system ace mpm control logic. upon release from the reset condition, the system ace mpm initiates the download procedure to the target fpgas. bitstrsel[2-0] input the bitstrsel pins determine which of the eight configuration data streams to download to the target fpga. status[3-0] output the status pins indicate the status of the system ace mpm control logic. figure 4: power pins ds087_04_090601 system ace mpm cfg_vcco configuration signals vccint1 vccint2 flash_vcco ctrl_vcco control signals slave-serial or slave-selectmap control circuits bitstrsel[0-2] sysclk sysreset 1.8v 3.3v cfg_vcco compatible with target fpgas ctrl_vcco compatible with control circuits system signals xilinx virtex-ii xilinx spartan-ii xilinx virtex-ii xilinx virtex-ii
system ace ? mpm solution 8 www.xilinx.com ds087 (v1.2) june 7, 2002 1-800-255-7778 advance product specification r pinout ta ble 6 provides system ace mpm pinout. unlisted bga sites are no connects. table 5: power and ground pins pin name pin type description vccint1 power 1.8v power supply pins for the virtex-e xcv50e configuration controller core. the 1.8v power supply should rise prior to or simultaneously to the flash_vcco, ctrl_vcco, and cfg_vcco power supplies.otherwise, the xcv50e device might draw excessive current. vccint2 power 3.3v power supply pins for the amd flash memory and the xc18v01 prom. flash_vcco power 3.3v power supply for the i/o banks connecting the virtex-e xcv50e controller to the amd flash memory. cfg_vcco power configurable power supply for the i/o banks on the target fpga configuration interface. connect this power pin to a voltage that is compatible with the target fpga configuration pins. ctrl_vcco power configurable power supply for the i/o banks on the system interface. connect this power pin to a voltage that is compatible with the system control and status monitor signals. gnd ground ground. table 6: system ace mpm pinout pin name xccacem16-bg388i XCCACEM32-BG388I xc cacem64-bg 388i a0 af8 af8 af8 a1 af4 af4 af4 a2 af3 af3 af3 a3 af2 af2 af2 a4 ae4 ae4 ae4 a5 ae3 ae3 ae3 a6 ae1 ae1 ae1 a7 ad2 ad2 ad2 a8 w1 w1 w1 a9 w2 w2 w2 a10 v1 v1 v1 a11 v2 v2 v2 a12 u1 u1 u1 a13 u2 u2 u2 a14 t1 t1 t1 a15 t2 t2 t2 a16 r25 r25 r25 a17 ad1 ad1 ad1 a18 ac2 ac2 ac2
system ace ? mpm solution ds087 (v1.2) june 7, 2002 www.xilinx.com 9 advance product specification 1-800-255-7778 r pin name xccacem16-bg388i XCCACEM32-BG388I xc cacem64-bg 388i a19 y1 y1 ac1 a20 n/a y2 y2 a21 n/a n/a y1 dq0 ad26 ad26 ad26 dq1 ac25 ac25 ac25 dq2 ab26 ab26 ab26 dq3 aa26 aa26 aa26 dq4 y26 y26 y26 dq5 w26 w26 w26 dq6 u26 u26 u26 dq7 t26 t26 t26 dq8 ad25 ad25 ad25 dq9 ac26 ac26 ac26 dq10 ab25 ab25 ab25 dq11 aa25 aa25 aa25 dq12 y25 y25 y25 dq13 w25 w25 w25 dq14 u25 u25 u25 dq15 t25 t25 t25 reset aa2 aa2 aa2 ce ae23 ae23 ae23 oe ae26 ae26 ae26 we aa1 aa1 aa1 ry/by ac1 ac1 n/a wp n/a ab2 ab2 acc n/a n/a ab1 flash_io_level r26 r26 r26 fcm_enable b7 b7 b7 fcmreset k26 k26 k26 devrdy n26 n26 n26 tck g26 g26 g26 tms a3 a3 a3 tdi f26 f26 f26 tdo a15 a15 a15 sysclk a9 a9 a9 sysreset b8 b8 b8 table 6: system ace mpm pinout (continued)
system ace ? mpm solution 10 www.xilinx.com ds087 (v1.2) june 7, 2002 1-800-255-7778 advance product specification r pin name xccacem16-bg388i XCCACEM32-BG388I xc cacem64-bg 388i bitstrsel[0] a6 a6 a6 bitstrsel[1] b5 b5 b5 bitstrsel[2] a5 a5 a5 status[0] a10 a10 a10 status[1] b9 b9 b9 status[2] b6 b6 b6 status[3] a7 a7 a7 cfg_data[0] j2 j2 j2 cfg_data[1] j1 j1 j1 cfg_data[2] h3 h3 h3 cfg_data[3] g2 g2 g2 cfg_data[4] h2 h2 h2 cfg_data[5] h1 h1 h1 cfg_data[6] j3 j3 j3 cfg_data[7] g3 g3 g3 cfg_mode[0] h26 h26 h26 cfg_mode[1] e1 e1 e1 cfg_mode[2] f2 f2 f2 cfg_cclk k1 k1 k1 cfg_busy g1 g1 g1 cfg_init k3 k3 k3 cfg_prog k2 k2 k2 cfg_done b3 b3 b3 cfg_writel1l1l1 cfg_cs[0] b1 b1 b1 cfg_cs[1] d1 d1 d1 cfg_cs[2] c1 c1 c1 cfg_cs[3] a1 a1 a1 ctrl_vcco a4, a16, a11 a4, a16, a11 a4, a16, a11 cfg_vcco m1, b4, f1 m1, b4, f1 m1, b4, f1 flash_vcco b14, j26, l26, af13, n1, af9 b14, j26, l26, af13, n1, af9 b14, j26, l26, af13, n1, af9 vccint1 c3, c7, c8, c9, c10, d6, d7, d8, d13, d14, e4, f4, k4, l2, m2, m3 c3, c7, c8, c9, c10, d6, d7, d8, d13, d14, e4, f4, k4, l2, m2, m3 c3, c7, c8, c9, c10, d6, d7, d8, d13, d14, e4, f4, k4, l2, m2, m3 table 6: system ace mpm pinout (continued)
system ace ? mpm solution ds087 (v1.2) june 7, 2002 www.xilinx.com 11 advance product specification 1-800-255-7778 r configuration overview the system ace mpm is engineered for high-speed config- uration of high-density fpgas. multiple configuration modes are supported to target fpgas including concurrent slave-serial mode, slave-selectmap mode, and slave-par- allel mode. the system ace mpm handles storage of up to eight separate configuration data sets. each data set can be optionally compressed to reduce the overall storage requirements. one default data set is automatically down- loaded to the target fpgas at system power-up. any one of the eight data sets can be selected to reconfigure the target fpgas at any time during system operation. configuration modes the system ace mpm supports high-speed fpga config- uration via the slave-serial or slave-selectmap configura- tion modes. the system ace mpm solution is a pre-engineered storage and delivery system with direct support for the high-density and high-speed configuration needs of the virtex-ii family. for example, the system ace mpm can configure a vir- tex-ii xc2v6000, which requires 19,759,968 configuration bits, via slave-serial mode in 300 milliseconds and via slave-selectmap mode in 130 milliseconds. in fact, the system ace mpm can configure two xc2v6000 devices concurrently via slave-serial mode in 300 milliseconds.see ta bl e 7 for maximum configuration bit rates. see ta bl e 8 for fpga configuration compatibility and cross-reference. see ta bl e 9 for system ace mpm and fpga configuration sig- nal cross-reference. pin name xccacem16-bg388i XCCACEM32-BG388I xc cacem64-bg 388i vccint2 aa23, ab4, ab23, ac4, ac11, ac12, ac13, ac18, ac19, ac20, d17, d18, d21, d22, d23, e23, h23, j23, n23, p23, r4, t4, u4, v26, y23 aa23, ab4, ab23, ac4, ac11, ac12, ac13, ac18, ac19, ac20, d17, d18, d21, d22, d23, e23, h23, j23, n23, p23, r4, t4, u4, v26, y23 aa23, ab4, ab23, ac4, ac11, ac12, ac13, ac18, ac19, ac20, d17, d18, d21, d22, d23, e23, h23, j23, n23, p23, r4, t4, u4, v26, y23 gnd a2, a8, a26, aa3, ab24, ad16, ad22, ae2, ae11, ae12, ae18, ae22, ae25, af1, af26, b15, b19, b22, b25, d4, d9, d10, d11, f23, g4, h25, j4, k23, l4, l11, l12, l13, l14, l15, l16, m4, m11, m12, m13, m14, m15, m16, m23, n11, n12, n13, n14, n15, n16, p2, p11, p12, p13, p14, p15, p16, r1, r11, r12, r13, r14, r15, r16, r23, t11, t12, t13, t14, t15, t16, t23, v25 a2, a8, a26, aa3, ab24, ad16, ad22, ae2, ae11, ae12, ae18, ae22, ae25, af1, af26, b15, b19, b22, b25, d4, d9, d10, d11, f23, g4, h25, j4, k23, l4, l11, l12, l13, l14, l15, l16, m4, m11, m12, m13, m14, m15, m16, m23, n11, n12, n13, n14, n15, n16, p2, p11, p12, p13, p14, p15, p16, r1, r11, r12, r13, r14, r15, r16, r23, t11, t12, t13, t14, t15, t16, t23, v25 a2, a8, a26, aa3, ab24, ad16, ad22, ae2, ae11, ae12, ae18, ae22, ae25, af1, af26, b15, b19, b22, b25, d4, d9, d10, d11, f23, g4, h25, j4, k23, l4, l11, l12, l13, l14, l15, l16, m4, m11, m12, m13, m14, m15, m16, m23, n11, n12, n13, n14, n15, n16, p2, p11, p12, p13, p14, p15, p16, r1, r11, r12, r13, r14, r15, r16, r23, t11, t12, t13, t14, t15, t16, t23, v25 table 6: system ace mpm pinout (continued)
system ace ? mpm solution 12 www.xilinx.com ds087 (v1.2) june 7, 2002 1-800-255-7778 advance product specification r table 7: maximum configuration bit rates configuration mode maximum system clock rate (sysclk) maximum configuration clock (cfg_cclk) rate (at max sysclk rate) average configuration clock rate (at max sysclk rate) maximum average combined configuration bit rate slave-selectmap 133 mhz 44 mhz 19 mhz 152 mb/s slave-serial 133 mhz 66 mhz 66 mhz 66 mb/s 2 concurrent slave-serial chains 133 mhz 66 mhz 66 mhz 133 mb/s (66 mb/s per chain) 3 - 4 concurrent slave-serial chains 133 mhz 66 mhz 38 mhz 152 mb/s (38 mb/s per chain) 5 - 8 concurrent slave-serial chains 133 mhz 66 mhz 19 mhz 152 mb/s (19 mb/s per chain) table 8: fpga configuration compatibility and cross-reference general description clock source data path delivery method virtex-ii virtex virtex-e spartan-ii serial configuration mode external 1-bit cascade through fpgas in daisy-chain style slave-serial slave-serial slave-serial parallel configuration mode external 8-bits chip-selected device on configuration data bus slave- selectmap selectmap slave-parallel table 9: system ace mpm and fpga configuration signal cross-reference fpga configuration signal system ace mpm virtex-ii virtex/ virtex-e spartan-ii configuration mode cfg_mode[2:0] m2, m1, m0 m2, m1, m0 m2, m1, m0 configuration clock cfg_clk cclk cclk cclk configuration data cfg_data[7:0] d7, d6, d5, d4, d3, d2, d1, din/d0 d7, d6, d5, d4, d3, d2, d1, din/d0 d7, d6, d5, d4, d3, d2, d1, din/d0 configuration reset cfg_prog prog_b program program configuration cfg_init init_b init init configuration busy cfg_busy busy busy busy
system ace ? mpm solution ds087 (v1.2) june 7, 2002 www.xilinx.com 13 advance product specification 1-800-255-7778 r slave-serial similar to the xilinx prom solution, the system ace mpm is a single package solution that supports the configuration of a single, cascaded chain of slave-serial fpgas. with the maximum configuration clock rate of 66 mhz, the system ace mpm is twice as fast as the nearest xilinx prom con- figuration solution in the slave-serial mode. the system ace mpm has additional support for concur- rently configuring multiple chains of slave-serial fpgas. multiple data output pins on the system ace mpm can con- currently supply bitstreams for two to eight slave-serial fpga chains. although each slave-serial chain has a max- imum configuration clock rate of 66 mhz, the maximum bit delivery rate of 66 mb/s is maintained across all concurrent slave-serial fpga chains up to the cumulative maximum of 152 mb/s. (152 mb/s is the maximum read rate from the amd flash memory in the system ace mpm.) in the concurrent slave-serial configuration mode, the bit- streams for the individual slave-serial chains are inter- leaved and optimized for concurrent configuration of two, four, or eight slave-serial fpga chains. configuration time and storage requirements are optimal when the data stream sizes are equivalent across all concurrent slave-serial fpga chains. the connectivity between the system ace mpm and slave-serial fpga chain is similar to the connectivity between a xilinx prom and a slave-serial fpga chain. all configuration signals between concurrent slave-serial fpga chains are common except that data for the first chain originates from the system ace mpm cfg_data[0] pin, the data for the second chain originates from the system ace mpm cfg_data[1] pin, etc. see figure 5 for a schematic of the slave-serial configuration signal connec- tions, and see ta bl e 1 0 for a list of the slave-serial configu- ration signals. the voltage compatibility for the system ace mpm configuration interface is configurable via the cfg_vcco pin. cfg_vcco should be connected to a voltage level that is compatible with the target fpgas. typi- cally, cfg_vcco is connected to either 3.3v or 2.5 v. con- sult the target fpga data sheet for an appropriate configuration signal voltage level. identical configuration of multiple target fpgas from one bitstream can be achieved through the appropriate configu- ration signal connections. figure 7 shows an example of two fpgas that are identically configured from a single bit- stream. ta bl e 1 0 provides the slave-serial configuration signals. configuration done cfg_done done done done selectmap/slave- parallel bus read/write signal cfg_write rdwr_b write write selectmap/slave- parallel bus chip select signal cfg_cs[3:0] cs_b cs cs table 9: system ace mpm and fpga configuration signal cross-reference fpga configuration signal system ace mpm virtex-ii virtex/ virtex-e spartan-ii
system ace ? mpm solution 14 www.xilinx.com ds087 (v1.2) june 7, 2002 1-800-255-7778 advance product specification r figure 5: system ace mpm configuration modes chip selects for up to 4 devices cs0 cs1 cs2 cs3 amd flash memory fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga fpga system ace configuration controller amd flash memory system ace configuration controller amd flash memory system ace configuration controller 152 mb/s selectmap bus 66 mb/s serial data stream up to 152 mb/s serial data stream 2 to 8 chains 66mb/s per chain serial data stream . . . ds087_05_091701 configuration modes selectmap slave-serial concurrent slave-serial figure 6: slave-serial configuration mode system ace mpm cfg_vcco cfg_data[0-7] * 3 cfg_mode[2] cfg_mode[1] cfg_mode[0] cfg_cclk cfg_init cfg_done cfg_prog busy fpga dout d0 m2 m1 m0 cclk init_b done prog_b dout d0 m2 m1 m0 cclk init_b done prog_b to chain0 cascaded fpgas cfg_data[1-7] * 3 to concurrent slave-serial fpga chains (1-7) (chain 0, device 0) fpga (chain 0, device 1) * 1 supply voltage to cfg_vcco that is compatible with the fpga configuration pins. * 2 only /wp on xccacem16; combined acc/wp on xccacem32; separate /wp and acc on xccacem64. * 3 use cfg_data[0] for systems with one slave-serial chain; use cfg_data[0-1] for systems with two concurrent slave-serial chains; use cfg_data[0-3] for systems with four concurrent slave-serial chains; use cfg_data[0-7] for systems with eight concurrent slave-serial chains. flash_io_level wp * 2 acc * 2 fcm_enable sysclk bitstrsel[0-2] status[0-3] sysreset clk source bitstrsel[0-2] 330 cfg_data[0] 4.7k 4.7k 3.3v 4.7 k cfg_vcco * 1 4.7 k ds087_05_091201
system ace ? mpm solution ds087 (v1.2) june 7, 2002 www.xilinx.com 15 advance product specification 1-800-255-7778 r figure 7: example slave-serial configuration for identically configured xilinx fpgas ds087_07_091701 cfg_vcco cfg_data[0] cfg_mode[2] cfg_mode[1] cfg_mode[0] cfg_cclk cfg_init cfg_done cfg_prog busy fpga d0 m2 m1 m0 cclk init_b done prog_b fpga d0 m2 m1 m0 cclk init_b done prog_b to identical fpgas * 1 supply voltage to cfg_vcco that is compatible with the fpga configuration pins. * 2 combined acc/wp on xccacem32; separate wp and acc on xccacem64. cfg_data[0] cfg_data[0] system ace mpm flash_io_level wp * 2 acc * 2 fcm_enable sysclk bitstrsel[0-2] status[0-3] sysreset clk source bitstrsel[0-2] 3.3v 4.7 k 4.7 k 330 4.7 k 4.7 k cfg_vcco * 1 table 10: slave-serial fpga configuration signals system ace mpm single slave-serial chain two slave-serial chains four slave-serial chains eight slave-serial chains cfg_mode[0] m0 on all fpgas m0 on all fpgas m0 on all fpgas m0 on all fpgas cfg_mode[1] m1 on all fpgas m1 on all fpgas m1 on all fpgas m1 on all fpgas cfg_mode[2] m2 on all fpgas m2 on all fpgas m2 on all fpgas m2 on all fpgas cfg_cclk cclk on all fpgas cclk on all fpgas cclk on all fpgas cclk on all fpgas cfg_prog prog_b on all fpgas prog_b on all fpgas prog_b on all fpgas prog_b on all fpgas cfg_init init_b on all fpgas init_b on all fpgas init_b on all fpgas init_b on all fpgas cfg_done done on all fpgas done on all fpgas done on all fpgas done on all fpgas cfg_data[0] din on first fpga of chain 0 din on first fpga of chain 0 din on first fpga of chain 0 din on first fpga of chain 0 cfg_data[1] din on first fpga of chain 1 din on first fpga of chain 1 din on first fpga of chain 1 cfg_data[2] din on first fpga of chain 2 din on first fpga of chain 2 cfg_data[3] din on first fpga of chain 3 din on first fpga of chain 3
system ace ? mpm solution 16 www.xilinx.com ds087 (v1.2) june 7, 2002 1-800-255-7778 advance product specification r although ta bl e 1 0 lists configuration signals for only one, two, four, or eight slave-serial chain systems, any number of slave-serial chains from one to eight are supported in the system ace software. the system ace software assigns the data streams for each slave-serial chain starting from cfg_data[0] up to cfg_data[n-1] where n is the number of slave-serial chains in the system. slave-selectmap/slave-parallel the system ace mpm conveniently supports high-speed, sequential configuration of up to four xilinx fpgas via the 8-bit-wide selectmap configuration bus or four spartan-ii devices via the 8-bit-wide slave-parallel bus. the system ace mpm generates a maximum configuration clock rate of 19 mhz. the maximum bit delivery rate is 152 mb/s. (152 mb/s is the maximum read rate from the amd flash mem- ory in the system ace mpm.) the connectivity between the system ace mpm and the fpgas on the selectmap bus is similar to the connectivity between a xilinx prom and a slave-selectmap fpga with the addition of the cfg_write and separate cfg_cs (chip select) signals. all configuration signals from the sys- tem ace mpm are common to all of the target fpgas on the selectmap bus, except that the cs_b signal of the first fpga must be connected to the system ace mpm cfg_cs[0] pin, and the cs_b signal of the second fpga must be connected to the system ace mpm cfg_cs[1] pin, etc. see figure 8 for a schematic diagram of the slave-selectmap configuration connections, and ta ble 1 1 for a list of the slave-selectmap connections for up to four target fpgas. the spartan-ii slave-parallel mode has the same structure and protocol as the slave-selectmap mode. therefore, the slave-selectmap figure and table apply to the spartan-ii slave-parallel mode with the appropriate signal name trans- lations noted in ta bl e 1 1 system ace mpm single slave-serial chain two slave-serial chains four slave-serial chains eight slave-serial chains cfg_data[4] din on first fpga of chain 4 cfg_data[5] din on first fpga of chain 5 cfg_data[6] din on first fpga of chain 6 cfg_data[7] din on first fpga of chain 7 table 10: slave-serial fpga configuration signals (continued)
system ace ? mpm solution ds087 (v1.2) june 7, 2002 www.xilinx.com 17 advance product specification 1-800-255-7778 r . figure 8: slave-selectmap configuration mode ds087_08_91001 cfg_vcco cfg_data[7:0] cfg_mode[2:0] cfg_cclk cfg_init cfg_done cfg_prog cfg_write busy cfg_cs[0-3] * 3 fpga cs_b d[7:0] m[2:0] cclk init_b done prog_b rdwr_b busy to selectmap fpgas (2-3) fpga cs_b d[7:0] m[2:0] cclk init_b done prog_b rdwr_b busy (cfg_cs[0]) (cfg_cs[1]) cfg_cs[1] cfg_cs[0] * 1 supply voltage to cfg_vcco that is compatible with the fpga configuration pins. * 2 combined acc/wp on xccacem32; separate /wp and acc on xccacem64. * 3 use cfg_cs[0] for systems with one slave-selectmap fpga ; use cfg_cs[0-1] for systems with two slave- selectmap fpgas; use cfg_cs[0-2] for systems with three slave-selectmap fpgas; use cfg_cs[0-3] for systems with four slave-selectmap fpgas. system ace mpm flash_io_level wp * 2 acc * 2 fcm_enable sysclk bitstrsel[0-2] status[0-3] sysreset clk source bitstrsel[0-2] 3.3v 4.7 k 4.7 k 330 4.7 k 4.7 k cfg_vcco * 1 table 11: slave-selectmap fpga configuration signals system ace mpm fpga 0 fpga 1 fpga 2 fpga 3 cfg_mode[0] m0 m0 m0 m0 cfg_mode[1] m1 m1 m1 m1 cfg_mode[2] m2 m2 m2 m2 cfg_cclk cclk cclk cclk cclk cfg_prog prog_b prog_b prog_b prog_b cfg_init init_b init_b init_b init_b cfg_busy busy busy busy busy cfg_done done done done done cfg_data[0-7] d[0-7] d[0-7] d[0-7] d[0-7] cfg_write rdwr_b rdwr_b rdwr_b rdwr_b cfg_cs [0] cs_b cfg_cs[1] cs_b cfg_cs[2] cs_b cfg_cs[3] cs_b
system ace ? mpm solution 18 www.xilinx.com ds087 (v1.2) june 7, 2002 1-800-255-7778 advance product specification r identical configuration of multiple target fpgas from a sin- gle bitstream can be achieved through the appropriate con- nections. see figure 9 for an example of two fpgas that are simultaneously configured from a single bitstream. the system ace software assigns bitstreams for the target fpgas in order, starting from the cfg_cs[0 ] pin through cfg_cs[n-1] pin where n is the number of slave-select- map devices in the system. n may be up to four devices. configuration data the configuration data sets for the target fpgas are stored in a standard, high-density flash memory unit in the system ace mpm. data storage the system ace mpm integrates a standard flash memory unit for storage of the configuration data sets. see ta bl e 1 2 . the system ace mpm product family offers data storage capacity up to 64 mb. see the flash memory vendor ? s data sheets for additional information about the flash memory unit in the system ace mpm. see table 13 for flash mem- ory data sheet references. figure 9: example slave-selectmap configuration for identically configured fpgas ds087_09_091001 cfg_vcco cfg_data[7:0] cfg_mode[2:0] cfg_cclk cfg_init cfg_done cfg_prog cfg_write busy cfg_cs[0] fpga cs_b d[7:0] m[2:0] cclk init_b done prog_b rdwr_b busy to identical selectmap fpgas fpga cs_b d[7:0] m[2:0] cclk init_b done prog_b rdwr_b busy cfg_cs[0] cfg_cs[0] system ace mpm * 1 supply voltage to cfg_vcco that is compatible with the fpga configuration pins. * 2 combined acc/wp on xccacem32; separate /wp and acc on xccacem64. flash_io_level /wp * 2 acc * 2 fcm_enable sysclk bitstrsel [0-2] status[0-3] sysreset clk source bitstrsel[0-2] 3.3v 4.7 k 4.7 k 330 4.7 k 4.7 k cfg_vcco * 1 table 12: flash memory storage system ace mpm flash device flash density flash speed grade flash organization xccacem16-bg388i amd am29lv160dt 16 mb 90 ns 1 m x 16-bit (or 2 m x 8-bit) XCCACEM32-BG388I amd am29lv320dt 32 mb 90 ns 2 m x 16-bit (or 4 m x 8-bit) xccacem64-bg388i amd am29lv641dh 64 mb 90 ns 4 m x 16-bit
system ace ? mpm solution ds087 (v1.2) june 7, 2002 www.xilinx.com 19 advance product specification 1-800-255-7778 r data set organization the flash memory data array begins with a data set direc- tory. there are eight directory entries that correspond to the binary value of the bitstrsel[2-0] setting. each directory entry is 16 bytes long. the main elements in a directory entry are: the configuration processing options for the data set, the starting address of the actual data set location, and the length of the data set in bytes. see figure 10 for details of the system ace mpm directory structure. the system ace software composes the entire flash mem- ory image and automatically calculates the directory infor- mation from the given data streams and user selected options. configuration data compression the system ace software gives the option to compress the data streams up to 50 percent. the system ace data stream is stored in the compressed format within the system ace mpm. the system ace mpm decompresses the data streams in real time delivery to the target fpgas. the compression performance is data-dependent. encrypted virtex-ii bitstreams are not compressible. configuration data security data security is available for virtex-ii bitstreams through the standard virtex-ii encryption technology. table 13: flash memory data sheet references system ace mpm flash device flash data sheet xccacem16-bg388i amd am29lv160dt http://www.amd.com/products/nvd/techdocs/22358.pdf XCCACEM32-BG388I amd am29lv320dt http://www.amd.com/products/nvd/techdocs/23579.pdf xccacem64-bg388i amd am29lv641dh http://www.amd.com/products/nvd/techdocs/22366.pdf figure 10: flash memory organization ds087_09_081501 dir entry 0 dir entry 1 dir entry 2 dir entry 3 dir entry 4 dir entry 5 dir entry 6 dir entry 7 0388h processing options (16 bits) start addr (lower 16 bits) start addr (upper 16 bits) data set byte size (lower 16 bits) start of data set 3 bitstrsel[2:0] = "011" data set directory data set byte size (upper 16 bits) reserved 16-bit word reserved 16-bit word 15(msb) 0(lsb) reserved 16-bit word flash memory array
system ace ? mpm solution 20 www.xilinx.com ds087 (v1.2) june 7, 2002 1-800-255-7778 advance product specification r configuration sequence the system ace mpm configuration sequence is automat- ically initiated at power-up for the initial system configuration and can be triggered later during system operation using the sysreset signal to reconfigure the system. the con- figuration sequence is as follows: 1. sample bitstrsel[2:0] pins to determine the data set to download. 2. pulse the cfg_program pin to clear the target fpgas and prepare them for configuration. 3. wait for the cfg_init pin to go high which indicates the target fpgas are ready to receive data. 4. find the data set from the data set directory structure in the flash memory. 5. deliver the data set to the target fpgas according to the configuration and processing options specified in the directory. 6. check for done to go high indicating a successful configuration. configuration control timing table 14 shows the configuration control timing details. table 14: control configuration timing symbol description min max units t sysreset sysreset min pulse 10 sysclk cycles t ssel bitstrsel[2:0] setup time to sysclk 1.1 ns t hsel bitstrsel[2:0] hold time from sysclk 0ns
system ace ? mpm solution ds087 (v1.2) june 7, 2002 www.xilinx.com 21 advance product specification 1-800-255-7778 r configuration data set selection the system ace mpm provides the opportunity to store up to eight separate configuration data sets for the target fpgas in the system. the system ace mpm bitstr- sel[0-2] pins determine which of the eight possible data sets to download. a data set is downloaded to configure the target fpgas automatically at system power-up, or a data set is downloaded to reconfigure the target fpgas upon activation of the system ace mpm sysreset pin. see ta ble 1 5 . at the beginning of a configuration sequence (initiated at power-up or via the sysreset pin), the system ace mpm samples the bitstrsel[2-0] pins to determine the data set to download. then, the system ace mpm downloads the data set to all target fpgas. the system ace mpm can be hardwired for power-up con- figuration. or, as shown in the example in figure 11 , the system ace mpm can be actively controlled and monitored by the microcontroller. configuration status the system ace mpm reports status through four status pins (status[3-0]). the status of the system ace mpm is available at all times. see table 16 for definitions of the sta- tus signals. ta bl e 1 7 provides the corrective action for status errors. table 15: configuration data set selection for bitstrsel[2:0] settings bitstrsel[2:0] selected data set [2] [1] [0] 0 0 0 data set 0 0 0 1 data set 1 0 1 0 data set 2 0 1 1 data set 3 1 0 0 data set 4 1 0 1 data set 5 1 1 0 data set 6 1 1 1 data set 7 figure 11: example microprocessor-based data set selection, configuration control, and configuration status monitor ds087_12_091001 microprocessor peripheral interface system ace mpm sysreset bitstrsel[0-2] status[0-3] ctrl_sysreset ctrl_ bitstrsel[0-2] ctrl_ status[0-3] table 16: status definitions status [3] status [2] status [1] status [0] status definition 0 0 0 0 reset ok; system ready 0 0 0 1 successful slave-serial or slave- selectmap configuration 0 0 1 0 configuration error (cfg_done did not go high) 0 0 1 1 decompress- ion error 0 100invalid controller state (internal error) 0 101invalid configuration data or blank flash memory 011xreserved 1 x x x mpm in wait state;. jtag flash commands (erase, blank-check, program, verify) can be issued.
system ace ? mpm solution 22 www.xilinx.com ds087 (v1.2) june 7, 2002 1-800-255-7778 advance product specification r programming the flash memory the system ace mpm provides two interfaces for access- ing the internal flash memory unit: the native flash mem- ory interface and the boundary scan port. the native flash memory interface provides direct access to the flash mem- ory pins for reading and writing. the boundary scan port provides indirect access to the flash memory pins via the boundary scan logic in the system ace mpm controller (xcv50e), whose boundary scannable pins are connected to the flash memory pins. see table 18 . drive fcm_enable low before using the native flash memory interface. system ace software the system ace software provides direct programming support via the xilinx parallel cable iii to the system ace mpm boundary scan port. the system ace software takes advantage of a flash memory programming engine that is integrated into the system ace mpm controller ? s boundary scan logic. boundary scan tools the system ace software can generate serial vector format (svf) files for system ace mpm operations. these svf files can be executed through a boundary scan test tool. automatic test equipment automatic test equipment (ate) vendors support in-system flash memory programming. the system ace mpm ? s native flash interface provides virtual access to every pin of the flash memory for the ate. during the programming operation, the ate must hold the fcm_enable signal on the system ace mpm low to ensure that there will no con- tention between the ate and the system ace mpm control- ler on the native flash interface signals. test access points are required for all of the native flash memory interface sig- nals and for the system ace mpm fcm_enable signal. third-party programmers third-party programmer vendors support stand-alone pro- gramming of the system ace mpm through the native flash memory interface. the system ace mpm program- ming times should be equivalent to the programming times for the stand-alone amd flash memory units. table 17: corrective action for status errors status error corrective action configuration error (cfg_done did not go high) check that all target fpga done pins are connected to cfg_done with external 330- ? pull-up resistor. decompression error perform sysreset sequence to re-initialize the system ace mpm controller and restart configuration. invalid controller state perform sysreset sequence to re-initialize the system ace mpm controller and restart configuration invalid configuration data or blank flash memory erase and reprogram the flash memory. perform sysreset sequence to re-initialize the system ace mpm controller and restart configuration. table 18: typical flash memory programming methods programming method/tool interface unit location phase(s) system ace software boundary scan in-system prototype development debug boundary scan tools boundary scan in-system development test production automatic test equipment native flash interface in-system test production programming method/tool interface unit location phase(s) third-party programmers native flash interface off-board pre- production microprocessor boundary scan or native flash interface in-system remote upgrade table 18: typical flash memory programming methods (continued)
system ace ? mpm solution ds087 (v1.2) june 7, 2002 www.xilinx.com 23 advance product specification 1-800-255-7778 r embedded microprocessor an embedded microprocessor can be used to remotely upgrade the system ace mpm data sets. the embedded microprocessor can program the flash memory in the sys- tem ace mpm using the native flash memory interface to directly control the flash memory or the four-wire boundary scan port. the native flash memory interface provides direct read access, as well as write access, to the flash memory. see the amd flash memory data sheet for the proper flash memory programming protocol. the fcm_enable signal on the system ace mpm must be held low during external access to the flash memory. otherwise, contention between the microprocessor and system ace mpm configuration controller can occur. the system ace software can generate an svf file for pro- gramming a system ace mpm flash memory through the system ace mpm boundary scan interface. the xilinx application note (xapp058) at: ( http://www.xilinx.com/xapp/xapp058.pdf ) provides reference c code and solutions for programming a device through boundary scan from an svf file. software support the standard xilinx design flow is followed for the develop- ment of the fpga design sets. the xilinx design software packages are used to develop the design from which . bit configuration file(s) are generated for each target fpga. the xilinx prom file formatter tool is then used to compile the . bit file(s) into a single image for downloading to a slave-serial chain of fpgas or to a single selectmap fpga. the output from the xilinx prom file formatter is an . mcs prom image. the set of . mcs prom images that configure all of the target fpga(s) connected to the system ace mpm is a called a design set. the system ace mpm can store up to eight data sets. the system ace software is used to compile multiple data sets into a single flash memory image. the flash memory image is stored as an .mpm file. the . mpm file is a standard intel hex (.mcs) file. the assignment of each data set to a target fpga chain or selectmap device is defined within the system ace software. the system ace software can also program the final flash memory image into the system ace mpm through a xilinx parallel cable iii, or it can generate an svf file for program- ming the system ace mpm using an alternate, boundary scan-based programming method. details of the system ace software are described in the system ace cf tech- nology software user guide . figure 12 shows the system ace mpm software flow. figure 12: system ace mpm software flow ds087_13_091701 bit file(s) xilinx design software/tools multiple hdl designs mcs file(s) mpm file prom file formatter system ace mpm flash memory system ace software foundation alliance foundation ise
system ace ? mpm solution 24 www.xilinx.com ds087 (v1.2) june 7, 2002 1-800-255-7778 advance product specification r ieee 1149.1 boundary scan the xilinx virtex-e xcv50e and xc18v01 proms in the system ace mpm support ieee 1149.1 boundary scan. although the amd flash memory does not support bound- ary scan, all signal pins on the amd flash memory and the mpm bg388 package are connected to boundary scanna- ble pins on the xcv50e device (with the exception of the xccacem64 ? s acc pin). thus, the system ace mpm sup- ports boundary scan for all significant signals on the sys- tem ace mpm via the xcv50e ? s boundary scan register. although the xc18v01 supports a boundary scan register, most of its signals are solely internal to the system ace mpm. signals from the xc18v01 device that reach the external bg388 sites are redundantly tied to the xcv50e device. thus, boundary scan can be effectively performed solely with the xcv50e boundary scan functions. see figure 13 . boundary scan test requirements the system ace mpm fcmreset signal drives the xcv50e /program pin. the active-low program pin on the xcv50e device resets the xcv50e ? s boundary scan test access port (tap) controller. the fcm_enable signal must not be driven low during boundary scan test. boundary scan test functionality is undefined during the system ace mpm initialization phase. therefore, boundary scan testing must wait until after the initialization phase is complete. a special system ace mpm boundary scan description language (bsdl) file is required for proper boundary scan test operation with the virtex-e xcv50e device. the xccacem16_bg388.bsd, xccacem32_bg388.bsd, and xccacem64.bsd files are available from the xilinx bsdl website under the software support pages at: http://www.support.xilinx.com figure 13: system ace mpm boundary scan mode 1 2 3 tdi tck tms tdo xcv50e tdi reset a0-a21 * 1 dq0-dq15 oe ce we wp ry/by * 3 xc18v01 tck tms tdo tdi system ace mpm tck tms tdo boundary scan register * 4 * * 2 acc/wp on xccacem32; xccacem64 has separate wp and acc pins. * 3 ry/by for xccacem16 and xccace32 only. * 4 boundary scan register is only conceptually depicted. see the system ace mpm bsdl file for accurate boundary-scan register information. reset a0-a21 * dq0-dq15 oe ce we acc/wp * ry/by * acc *2 most xc18v01 signals remain inside the mpm except a few status signals shared with the xcv50e xcv50e boundary scan can scan most mpm signal pins for board test ds087_14_091701 a21 for xccacem64 only; a20 for xccacem32 and xccacem64 only. * 1 amd flash
system ace ? mpm solution ds087 (v1.2) june 7, 2002 www.xilinx.com 25 advance product specification 1-800-255-7778 r tap t iming see figure 14 for boundary scan tap timing requirements. tap ac param eters ta ble 1 9 provides boundary scan tap ac characteristics. figure 14: boundary scan tap timing diagram tck t ckmin t mss tms tdi tdo t msh t dih t dov t dis ds087_15_091001 table 19: boundary scan tap ac characteristics symbol parameter min max units t ckmin1 tck minimum clock period 100 - ns t ckmin2 tck minimum clock period, bypass mode 50 - ns t mss tms setup time 10 - ns t msh tms hold time 25 - ns t dis tdi setup time 10 - ns t dih tdi hold time 25 - ns t dov tdo valid delay - 11 ns
system ace ? mpm solution 26 www.xilinx.com ds087 (v1.2) june 7, 2002 1-800-255-7778 advance product specification r absolute maximum ratings ta ble 2 0 provides absolute maximum ratings. recommended operating conditions ta ble 2 1 provides the recommended operating conditions. table 20: absolute maximum ratings symbol description min max units vccint1 1.8v supply voltage relative to gnd -0.5 2.0 v vccint2 3.3v supply voltage relative to gnd -0.5 4.0 v flash_vcco flash interface power supply -0.5 4.0 v cfg_vcco configuration interface power supply -0.5 4.0 v ctrl_vcco system interface power supply -0.5 4.0 v v in input voltage with respect to gnd -0.5 4.0 v v ts voltage applied to 3-state output. -0.5 4.0 v vccint1_r longest 1.8v supply voltage rise time 0 v ? 1.71 v 50 ms t stg storage temperature (ambient) -40 125 c table 21: recommended operating conditions symbol description min max unit vccint1 1.8v supply voltage relative to gnd 1.8 - 5% 1.8 +5% v vccint2 3.3.v supply voltage relative to gnd 3.0 3.6 v
system ace ? mpm solution ds087 (v1.2) june 7, 2002 www.xilinx.com 27 advance product specification 1-800-255-7778 r quality and reliability characteristics dc characteristics over operating conditions ta ble 2 2 provides dc characteristics over operating conditions. dc input and output levels over operating conditions three of the primary interfaces (the boundary scan inter- face, the system control interface, and the target fpga interface) to the system ace mpm have i/o level compati- bility control pins. see figure 2 and figure 4 . flash_vcco controls the internal flash memory interface and the boundary scan interface. flash_vcco must be connected to a 3.3v power supply. the boundary scan ports (tck, tms, tdi, and tdo) and the internal flash memory interface pins follow the 3.3v input and output level specification. ctrl_vcco controls the system control interface, and cfg_vcco controls the target fpga inter- face. the input and output level specifications for the sys- tem control and target fpga interface pins depend on the voltage connection to the ctrl_vcco and cfg_vcco pins. see ta bl e 2 3 for the input and output level specifica- tions for each vcco voltage level. ac characteristics over operating conditions ta ble 2 4 provides the ac characteristics over operating conditions. table 22: dc characteristics over operating conditions symbol description min max unit v drint1 data retention vccint1 voltage 1.5 v i ccint1q quiescent v ccint1 supply current 200 ma i ccint2q quiescent v ccint2 supply current 40 ma i l input leakage current -11 +11 a c in input capacitance 10 pf c out output capacitance 10 pf table 23: dc input and output levels over operating conditions vcco voltage level v il , min v il , max v ih , min v ih , max v ol , max v oh , min i ol , max i oh , min 3.3 v -0.5 v 0.8 v 2.0 v 3.6 v 0.4 v 2.4 v 24 ma -24 ma 2.5 v -0.5 v 0.7v 1.7 v 2.7 v 0.4 v 1.9 v 12 ma -12 ma 1.8 v -0.5 v 35% vcco 65% vcco 1.95 v 0.4v vcco - 0.4 v 8 ma -8 ma table 24: ac characteristics over operating conditions timing parameter description min max unit f sys maximum sysclk frequency 133 mhz t scl sysclk low time 3.75 ns t sch sysclk high time 3.75 ns t sysreset minimum sysreset pulse time 10 sysclk cycles t cyc cfg_cclk period 66.5 mhz t lc cfg_cclk low time 7.5 ns t hc cfg_cclk high time 7.5 ns
system ace ? mpm solution 28 www.xilinx.com ds087 (v1.2) june 7, 2002 1-800-255-7778 advance product specification r quality and reliability characteristics ta ble 2 5 provides quality and reliability characteristics. notes: 1. see amd flash memory data sheet. system ace mpm power-on power supply requirements the system ace mpm requires two supply voltages: 1.8v and 3.3v. the 1.8v supplies power to the embedded xcv50e configuration controller core. the 3.3v supplies power to remaining xcv50e power pins and to all other devices. the 3.3v supply must be applied after or simulta- neous to the 1.8v supply. the embedded xcv50e and xc18v01 require monotonic power supply ramps. the xcv50e requires the 1.8v supply to ramp to nominal volt- age in less than 50 milliseconds. see figure 15 . before any programming operations can be performed, the programmer must wait for the xcv50e ? s initialization phase to complete. the programmer may wait for either the maxi- mum initialization time or for the system ace mpm devrdy signal to go high which indicates the end of the initialization phase. after the initialization phase is com- plete, the device is ready for operation. see ta bl e 2 6 for power-on power supply requirements. table 25: quality and reliability characteristics symbol description min max unit t dr data retention 20 (note 1) years n pe program/erase cycles 1 million (note 1) cycles v esd electrostatic discharge (hbm) 1500 volts figure 15: power-on power supply requirements table 26: power-on power supply requirements parameter description minimum maximum t v1 1.8v power supply ramp 0-1.8 v 2 ms 50 ms t v1v2 1.8v to 3.3v power sequence delay 0 ms t rdy initialization time after 3.3v or fcmreset 250 ms t rst system ace mpm controller reset 300 ns i 1.8 v 1.8v supply current 2 a ds087_16_060701 vccint1=1.8v vccint2=3.3v devrdy fcmreset t v1 t v1v2 t rdy 1.8v 0.0v 3.3v 0.0v t rst t rdy
system ace ? mpm solution ds087 (v1.2) june 7, 2002 www.xilinx.com 29 advance product specification 1-800-255-7778 r ordering information valid ordering combinations revision history the following table shows the revision history for this document. ds087_17_091001 xccacem16 bg388 i device number xccacem16 xccacem32 xccacem64 package type bg388 = 388-site ball grid array operating range/processing i = industrial (ta = -40? to +85? c) valid ordering combinations description xccacem16bg388i 16 mb system ace mpm xccacem32bg388i 32 mb system ace mpm xccacem64bg388i 64 mb system ace mpm date version revision 09/25/01 1.0 initial xilinx release. 01/18/02 1.1 minor edits done. 06/07/02 1.2 added "virtex series fpgas" and "virtex-ii series platform fpgas" to the summary.

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